-------------------------------------------------------------------------------
-- Title      : 
-- Project    : 
-------------------------------------------------------------------------------
-- File       : top.vhd
-- Author     :   <Rome@ROME-PC>
-- Company    : 
-- Created    : 2014-03-11
-- Last update: 2014-03-29
-- Platform   : 
-- Standard   : VHDL'87
-------------------------------------------------------------------------------
-- Description: 
-------------------------------------------------------------------------------
-- Copyright (c) 2014 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author  Description
-- 2014-03-11  1.0      Rome    Created
-------------------------------------------------------------------------------

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity top is
  
  port (
    clk_50m_i             : in    std_logic;
    rst_ext_n_i           : in    std_logic;
    w5200_rst_n_o         : out   std_logic;
    w5200_pwdn_o          : out   std_logic;
    w5200_int_n_i         : in    std_logic;
    w5200_cs_n_o          : out   std_logic;
    w5200_sclk_o          : out   std_logic;
    w5200_dout_o          : out   std_logic;
    w5200_din_i           : in    std_logic;
    -- iic
    i2c_wp_o              : out   std_logic;
    i2c_scl_o             : out   std_logic;
    i2c_sda_io            : inout std_logic;
    i2c_master_scl_io : inout std_logic := '0';  --     i2c_master.scl_pad_io
    i2c_master_sda_io : inout std_logic := '0'  --               .sda_pad_io

    );

end top;

architecture behave of top is

  component pll80m
    port (
      areset : in  std_logic := '0';
      inclk0 : in  std_logic := '0';
      c0     : out std_logic;
      locked : out std_logic);
  end component;

  signal rst_n_l   : std_logic := '0';
  signal clk_sys_l : std_logic := '0';

  component sequencer
    generic (
      RESET_CNT : integer);
    port (
      clk_sys_i   : in  std_logic;
      rst_ext_n_i : in  std_logic;
      rst_n_o     : out std_logic);
  end component;

  component my_nios
    port (
      clk_clk               : in    std_logic := '0';
      spi_0_external_MISO   : in    std_logic := '0';
      spi_0_external_MOSI   : out   std_logic;
      spi_0_external_SCLK   : out   std_logic;
      spi_0_external_SS_n   : out   std_logic;
      i2c_scl_o_export      : out   std_logic;
      pio_input_export      : in    std_logic;
      i2c_sda_io_export     : inout std_logic := '0';
      reset_reset_n         : in    std_logic := '0';
      i2c_master_scl_pad_io : inout std_logic := '0';  --     i2c_master.scl_pad_io
      i2c_master_sda_pad_io : inout std_logic := '0'  --               .sda_pad_io

      );
  end component;
  
begin  -- behave

  pll80m_1 : pll80m
    port map (
      areset => '0',                    --not rst_ext_n_i,
      inclk0 => clk_50m_i,
      c0     => clk_sys_l,
      locked => rst_n_l);

--  sequencer_1 : sequencer
--    generic map (
--      RESET_CNT => 2000)
--    port map (
--      clk_sys_i   => clk_sys_l,
--      rst_ext_n_i => rst_n_l,
--      rst_n_o     => w5200_rst_n_o);

  w5200_rst_n_o <= '1';
  w5200_pwdn_o  <= '0';
  i2c_wp_o      <= '0';

  my_nios_1 : my_nios
    port map (
      clk_clk               => clk_sys_l,
      spi_0_external_MISO   => w5200_din_i,
      spi_0_external_MOSI   => w5200_dout_o,
      spi_0_external_SCLK   => w5200_sclk_o,
      spi_0_external_SS_n   => w5200_cs_n_o,
      i2c_scl_o_export      => i2c_scl_o,
      pio_input_export      => w5200_int_n_i,
      i2c_sda_io_export     => i2c_sda_io,
      reset_reset_n         => '1',
      i2c_master_scl_pad_io => i2c_master_scl_io,
      i2c_master_sda_pad_io => i2c_master_sda_io
      );

end behave;
